In the microcomputer field, it is often advantageous to have as many as possible of the primary functions of computing located on a single chip. Because of the desirability to minimize the area occupied and power dissipated by circuits implementing these functions, a design approach which meets these criteria presents significant advantages over more conventional approaches. Therefore low-power circuits or parts of circuits which can perform a dual function are particularly desirable. One-chip microcomputers usually contain read-only memory (ROM) and random-access memory (RAM). These memories are often addressed by the same address terms which makes it possible to share part of the address decoding structure. Such a structure is described in U.S. Pat. No. 3,806,880 to Spence entitled Multiplexing System for Address Decode Logic, assigned to Rockwell International, assignee of the present invention.
Heretofore, N-channel microcomputers have utilized so-called "static" logic techniques, which tend to consume relatively high power. A desired feature of short ROM and RAM access times, further requires decoding schemes which also tend to consume relatively large amounts of power. Thus, the subject invention relates to an improved address decoder circuit, particularly adaptable to a N-channel single-chip microcomputer, in which the decoder logic is shared between two memories, typically a ROM and a RAM, and in which the decoder circuit utilizes so-called "ratioless" logic techniques resulting in relatively low-power consumption.